FIELD OF THE INVENTION
This invention concerns a configuration for self-referencing a ferroelectric memory cell which is formed of a ferroelectric storage capacitor with a cellplate and a transfer transistor. The ferroelectric memory cell is provided in a memory cell array controlled via word lines and bit lines. The ferroelectric storage capacitor is provided between a cellplate line and the transfer transistor. In order to perform a self-referencing with an evaluator circuit, the memory cell is written-in and read-out again after a read process for determining a reference voltage.
As illustrated in FIG. 18, in prior art ferroelectric memories memory cells of ferroelectric storage capacitors Cs0, Cs1 and transfer transistors T are provided between bit lines BL and word lines WL0, WL1. The cellplates of the memory cells can be connected to one another either parallel to the bit lines, as shown in FIG. 18, or parallel to the word lines WL0, WL1, but can also be provided such that they are connected in both directions.
On reading out the content of such a ferroelectric memory cell the bit line BL acquires a read voltage of U.sub.L1 or U.sub.L0 depending on whether a "1" or a "0" is read out (cf. also FIG. 17). The voltage difference between the read voltages U.sub.L1 and U.sub.L0 is normally in the region of 100 mV.
The task of an evaluator circuit--also known as an "evaluator"--is to detect the read voltage U.sub.L on the bit line BL as "1" (i.e. U.sub.L1) or "0" (i.e. U.sub.L0) and to amplify it accordingly. The detection takes place through comparison of the read voltage U.sub.L with a reference voltage U.sub.R. If the read voltage is greater than the reference voltage U.sub.R, a "1" is detected; if it is smaller than the reference voltage U.sub.R a "0" is detected.
In the prior art, in most cases this is achieved through generating the reference voltage on a reference bit line BL by reading out the content of a reference cell formed of a ferroelectric storage capacitor C and a transfer transistor T, whereby this reference cell is dimensioned and/or connected such that the reference voltage U.sub.R is produced in a suitable way.
It is also important that the reference voltage U.sub.R be exact to within a few mV and as close as possible to the middle position between the read voltages U.sub.L1 for "1" and U.sub.L0 for "0".
This requirement, however, causes considerable problems in the generation of the reference voltage U.sub.R during operation of the ferroelectric memory:
(a) The read voltage U.sub.L of the ferroelectric memory cells and the reference voltage U.sub.R of the reference cells are already scattered simply as a result of the manufacturing process, which cannot proceed in exactly the same way for all memory cells.
(b) Depending on the number of write and read cycles, the electrical characteristics of the ferroelectric memory cells and the reference cells change as a result of the "aging" characteristics (hysteresis curve becomes narrower), "fatigue" (hysteresis curve rotates) and "imprint" (hysteresis curve is displaced up or down), whereby this aging process progresses differently for the two types of cell.
As a consequence of the above problems (a) and (b), the read voltage U.sub.L and/or the reference voltage U.sub.R can be displaced to such an extent that correct evaluation of the read voltage U.sub.L as a "1" or a "0" during operation of the ferroelectric memory is no longer possible.
In order to avoid the above difficulties, a self-referencing of a memory cell is described in the article "A Self-Reference Read Scheme for a 1T/1C FeRAM", by J. Yamada et. al., 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 238 and 239, according to which the problem of differential aging of a memory cell and a reference cell is avoided. In this conventional self-referencing method, however, circuit measures such as different bit line capacities or evaluator circuits are used for generating the reference voltage, which results again in a dependence on the aging of the memory cells.